Consider a single-level cache with an access time of 3 ns, a line size of 32 bytes, and a hit ratio of H = 0.95. Main memory uses a block transfer capability that has a first word (2 bytes) access time of 40 ns and an access time of 5 ns for each word thereafter. (a) What is the access time when there is a cache miss? Assume that the cache waits until the line has been fetched from main memory and then re-executes for a hit. (b) Suppose that increasing the line size to 64 bytes increases the H to 0.97. Does this reduce the average latency?
