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Alasian

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February 3, 2009
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April 3, 2010

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The physical representation of logic gates

Alasian replied to seriously disabled's topic in Computer Science

It is set up so when it is above 5V it is a 1. If it is below for example 1.5V it is a 0. In between 1.5V and 5V it is an invalid state. This is how CMOS work and a chip which holds some gates is feeding the input of the gates whatever the CMOS translates to it, either 1 or 0.
- February 4, 2009
- 10 replies

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