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andWindsor15

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  1. Hi everyone, Can anyone help me to answer the question below? I would really appreciate it if you could help me. I have been searching for a solution for this question in books but could not find a proper explanation of how these things work. A processor has 24 registers, uses 8-bit immediates, and has 36 different instructions (corresponding to 36 operation codes) in its instruction set. These 36 instructions are classified into 4 types as listed below: Type-A: takes 2 source registers, uses 1 destination register; Type-B: takes 1 source register, uses 1 destination register; Type-C: takes 1 source register, 1 immediate, uses 1 destination register; Type-D: takes 1 immediate, uses 1 destination register. Assume that the Instruction Set Architecture requires that all instructions be a multiple of 8 bits (1 byte) in length, and the operation codes (opcodes) are of fixed length. a) How many bytes do we need to use to encode the Type-A instruction? b) How many bytes do we need to use to encode the Type-C instruction?
  2. Hi SarK0Y, Thank you so much for your answer. Can you help me answer this question please? A processor has 24 registers, uses 8-bit immediates, and has 36 different instructions (corresponding to 36 operation codes) in its instruction set. These 36 instructions are classified into 4 types as listed below: Type-A: takes 2 source registers, uses 1 destination register; Type-B: takes 1 source register, uses 1 destination register; Type-C: takes 1 source register, 1 immediate, uses 1 destination register; Type-D: takes 1 immediate, uses 1 destination register. Assume that the Instruction Set Architecture requires that all instructions be a multiple of 8 bits (1 byte) in length, and the operation codes (opcodes) are of fixed length. a) How many bytes do we need to use to encode the Type-A instruction? b) How many bytes do we need to use to encode the Type-C instruction?
  3. Hi, Can anyone answer the question below? A processor has a 32-bit instruction format with the following fields: opcode: 8bits ra: 6 bits rb: 6 bits rc: 6 bits rd:6 bits where ra, rb and rc specify three input registers and rd specifies one destination register. Assume the processor uses a register file (i.e. a memory block with the smallest size as required) to store the identifications of all registers, how many registers could this file hold in theory,and why? Thank you very much
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