Strange Posted November 4, 2018 Posted November 4, 2018 9 hours ago, Menan said: I do not establish such things, but the current best estimate for an entanglement speed is three trillion meters per second or four times light speed. So somebody dig up Albert and have him start the whole thing over. Effectively instantaneous between any two Earth points https://futurism.com/chinese-physicists-measure-speed-of-quantum-entanglement-2/ ! Moderator Note Please stick to the topic of this thread (capacitors).
studiot Posted November 4, 2018 Posted November 4, 2018 (edited) 46 minutes ago, studiot said: One of the main timing problems in IC design is the time it takes for signals to propagate along wires between components. This time delay is determined by the capacitance and resistance of the wires. It is this particularly I am taking issue with. Yes unwanted capacitance can introduce many unwanted effects, viz alteration of the bode plot, oscillation, instability, loss of sensitivity at certain frequencies to name but a few. But I don't know of any circuit where stray capacitance in the wires introduces propagation delay. Wanted capacitance in the form of circuit capacitors (eg a bucket brigade device) are different and designed to provide propagation delay in the circuit as a whole. Inductance, on the other hand is dependent on the length of track, amongst other things. So it is perfectly possible for a (longer) track that leads to a gate on the other side of an IC to introduce sufficient inductive delay to break synchronicity, even though the longer track may have lower capacitance due to its path. This is well known and provides the limit of speed in parallel processing chips. Edited November 4, 2018 by studiot
Strange Posted November 4, 2018 Posted November 4, 2018 12 minutes ago, studiot said: But I don't know of any circuit where stray capacitance in the wires introduces propagation delay. Well, I am happy to admit that I relied on others to do the analog modelling to confirm timing. (And it is a couple of decades since I did any design work.) But I was under the impression that some of the parasitic capacitance came from the wires . But maybe my recollection is wrong and it was mainly the resistance and inductance of the wires plus the load capacitance. That doesn't change the original point that capacitance has an effect on the timing in circuits, whether that is their deliberate use in a tuned circuit or as parasitic capacitance that has to be accounted for. Edit: and I realise my use of "propagation delay" may not be correct either. The main factor we were concerned with was slew rate or rise time.
studiot Posted November 4, 2018 Posted November 4, 2018 (edited) 39 minutes ago, Strange said: Well, I am happy to admit that I relied on others to do the analog modelling to confirm timing. (And it is a couple of decades since I did any design work.) But I was under the impression that some of the parasitic capacitance came from the wires . But maybe my recollection is wrong and it was mainly the resistance and inductance of the wires plus the load capacitance. That doesn't change the original point that capacitance has an effect on the timing in circuits, whether that is their deliberate use in a tuned circuit or as parasitic capacitance that has to be accounted for. Edit: and I realise my use of "propagation delay" may not be correct either. The main factor we were concerned with was slew rate or rise time. Yes unwanted (my general term for stray, parasitic etc) capacitance is generally in parallel with the signal. This is how it affects rise time, slew rate, changes true timing of a subcircuit which has an RC timing function, degrades or even removes hf components in signals and so forth. Capacitors in series with the signal, eg my bucket brigade delay lines will offer a propagation delay due to the capacitance. But once a circuit is wired up how do you get an unwanted capacitor in series? But I think we are agreed that unwanted capacitance can seriously upset the health of a circuit in many ways. Restored after a propagation glitch The one good thing about SF editor Edited November 4, 2018 by studiot
Strange Posted November 4, 2018 Posted November 4, 2018 4 hours ago, studiot said: Yes unwanted (my general term for stray, parasitic etc) capacitance is generally in parallel with the signal. This is how it affects rise time, slew rate, changes true timing of a subcircuit which has an RC timing function, degrades or even removes hf components in signals and so forth. Exactly. 4 hours ago, studiot said: Capacitors in series with the signal, eg my bucket brigade delay lines will offer a propagation delay due to the capacitance. But once a circuit is wired up how do you get an unwanted capacitor in series? Who said you could?
swansont Posted November 4, 2018 Posted November 4, 2018 5 hours ago, Strange said: ! Moderator Note Please stick to the topic of this thread (capacitors). ! Moderator Note Posts discussing entanglement have been moved back to the parent thread.
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