Is a Ternary Computer Possible?

[QuantumT]

Would it be technically possible to make a ternary (3 bit) computer? Instead of the basic "on or off" in our standard binary ones.

I imagine this might be done by having one extra state added beside on and off.
We could call it dormant or standby mode. Dormant/standby would then be neither fully on or fully off.

 

Edit: I would also imagine that such a computer would be incapable of communicating with binary computers, and be of less use, due to its isolation.

Edit #2: I see now that I have been searching with the wrong keywords, and that such computers have been made: https://en.wikipedia.org/wiki/Ternary_computer

Sorry for the inconvenience. Mods may terminate this, if deemed redundant.

Edited March 29, 2019 by QuantumT

[wtf]

Sure. https://en.wikipedia.org/wiki/Balanced_ternary

[Sensei]

5 hours ago, QuantumT said:

Edit: I would also imagine that such a computer would be incapable of communicating with binary computers, and be of less use, due to its isolation. 

In how many states single bit is stored internally is independent subject from communication. Ternary computer would have to use TCP/IP to communicate with other currently existing computers.

BCD (Binary-coded decimal) is an example of data format which uses less states 0-9 than available in hexadecimal digit (0-15). Some states are simply ignored/illegal.

Ternary computer to simulate binary system could simply use states 0-1 and ignore state 2, in each 3-bit. Analogous to BCD implementation.

 

Edited March 30, 2019 by Sensei

[Sensei]

Normal computer applications have all the time to do conversion from binary to decimal and from decimal to binary. To show results of computation in human readable format, and parse human numerical input to internal binary format.

int number = 123;

printf( "%d", number );

scanf( "%d", &number );

 

Edited March 30, 2019 by Sensei

[Strange]

Multiple levels are difficult to manage and (in current logic technologies) use more power. 

However, flash memories use multiple levels of charge to store 2 or more bits per cell. This gives greater storage density at the cost of reduced speed