Digital Electronics and "SR Flip-Flops"

[Rasori]

I've been doing some digital electronics in my studies lately, and I'm just not getting this part. Well, rather, I can do all the work just fine, I'm just not understanding something that my lecturer claims is unimportant.

 

I'm sure many of you know what it is, but to make the problem I have clear I'm going to explain:

 

S NAND (NOT)Q = A = Q

R NAND Q = B = (NOT)Q

They both seem simple enough, but I'm not getting how it /starts/. On start-up, S and R are defined, but I can't fathom how S[or R] NAND (NULL) gives a value at all.

 

My best guess would be to set S and R = logic 0 to start with, so that regardless of (NULL) the NAND would be logic 1, but A and B can't be the same value by definition of the SR Flip-Flop. Is it acceptable to break that rule for this initialization or is something else going on here?

[darkenlighten]

So are you talking about a SR Latch without out a control value and if so can you can explain a little better, what you are unclear about?

 

Because I am not sure what you are referring to when you talk about Null? Do you mean when S = 1 and R = 1? Which is when it is undefined...

[Rasori]

I'm actually specifically unclear about the start-up. According to a brief google search, yes, latch is what I'm talking about.

 

Null is my own terminology, I guess (I've been playing with programming too much lately). Basically, when a system containing an S-R Latch is first started (batteries freshly inserted and everything), I don't understand how the NAND gates have any output at all, as they're based off of two inputs and only receiving one. The second input to the NAND gate is inherently dependent on the past values of the other input, of which there are none.

 

As I think about it more and more I slowly come up with my own reasoning--the best idea I've had so far is that a two-input NAND gate with one of the inputs being neither logic 0 or logic 1 (logic 0 inherently has some reading, it's not absolutely empty if I understand correctly) thinks of itself as simply an inverter on the one valid input. Is that right?

[darkenlighten]

I see. The initial state is not known until time has elapsed, of course a very small time. So I believe the second input you are talking about that the NAND Gates are receiving at t = 0 is just a logic 0 or 0 volts, until time has elapsed and it is receiving the desired input/output combination.

 

And even though this seems like a non-casual system (a system that does depend on an input at t greater than your current t), it does not change once the inputs are set. You are really only getting a delay, which you will learn more about in labs hopefully, though an easy idea to consider due to physical restrictions.