Computer Architecture Help

[Maxx]

Okay so we went over Cache Memory today in lecture and I thought I was doing okay. However this homework assignment has be stumped. So if anyone can point me into the right direction that would be great!

 

 

1. Suppose memory block size is 4 words (1 byte/word) and memory addresses are 32 bits. How many total bits (data + overhead) are required to implement a direct-mapped cache containing 64KB of data?

 

What I did:

 

64k byes = 16 k words (64/4)

log (2) 16k = 14 (2^14 = 16384), 14 bit index

tag = 32-14-2 = 16 bits

 

Total: 32 + 16 + 1 = 49 bits

 

2^14 * 49 = 784 kbits = 98kb

 

I am not even sure if I did any of this right to be honest. I am following some examples in the book but they are very hard to follow. Anyone know anything about this?

 

 

 

2. Suppose main memory contains 512 M words (1 byte/word), with 128 words per block. The system incorporates a set associative cache consisting of 64 lines divided into four-line sets. Show the memory address format.

 

I am not sure where to start here for this one. A little guidance would be appreciated.

 

Thanks for any help

 

-Max