A 4-stage pipeline problem

[shelly_cooper]

A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanosecondsrespectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, what will be the total time taken to process 1000 data items on this pipeline?

[Enthalpy]

Knowing that your teacher took 30 years to propagate such values from his studies to yours, how many students will go through his pipeline of inept data before he eventually retires?

 

Presently, the time unit is PICOseconds. And engineering IS all about actual values.

 

By the way, a register doesn't have "a delay". It has at least a setup time and a propagation time.

And nothing tells you the actual clock frequency of this archaeotechnological machine - only a maximum frequency, if only you had sensible register data.

 

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Just for fun: the Cray-1 (1976!) had a pipeline for its floating-point adder where one register was missing. This was the critical path for the clock frequency of the whole machine, and the designers found that the propagation time was precise, predictable and stable enough (and equal for rising and falling edges, thanks to ECL) that the intermediate data was stored in the propagation time of the intermediate gates. A bit like a machine gun fires new rounds before the previous ones hit the target. By sorting out the gates before assembly, it did work and gained >10% clock frequency. ¡Ole!