Instruction Set Architecture

[andWindsor15]

Hi,

 

Can anyone answer the question below?

 

 

A processor has a 32-bit instruction format with the following fields:

opcode: 8bits ra: 6 bits rb: 6 bits rc: 6 bits rd:6 bits

 

where ra, rb and rc specify three input registers and rd specifies one destination
register. Assume the processor uses a register file (i.e. a memory block with
the smallest size as required) to store the identifications of all registers, how many registers could this
file hold in theory,and why?

 

Thank you very much

[SarK0Y]

*you may encode maximally 2^6 registers, if "rb==ra==rc==rd" case is possible.

*if ra, rb, rc, rd define independent sets of registers, then 4*(2^6).

[andWindsor15]

Hi SarK0Y,

 

Thank you so much for your answer. Can you help me answer this question please?

 

A processor has 24 registers, uses 8-bit immediates, and has 36 different instructions
(corresponding to 36 operation codes) in its instruction set. These 36
instructions are classified into 4 types as listed below:

Type-A: takes 2 source registers, uses 1
destination register;

Type-B: takes 1 source register, uses 1
destination register;

Type-C: takes 1 source register, 1 immediate,
uses 1 destination register;

Type-D: takes 1 immediate, uses 1 destination
register.

 

Assume that the Instruction Set Architecture requires that all instructions be a multiple of 8 bits (1 byte) in
length, and the operation codes (opcodes) are of fixed length.

a)
How many bytes do we need to use to
encode the Type-A instruction?

b)
How many bytes do we need to use to
encode the Type-C instruction?

[andWindsor15]

why 2^6?

[SarK0Y]

here takes a place following formula: log2(I) + N*log2® + N1*Im.

 

I -- number of instructions to encode.

R -- total number of registers.

N -- number of taken registers for given operation (source/dest).

N1 -- number of immediates.

Im -- length of immediate (in bits).

-------------------------

Actually, it's right for flat designs. For example, non-flat scheme could provide next logic:

 

ra (register) contains a reference to RA (register), RA could contain opcode/value/immediate. In other words, RA's go as extension registers to provide more memory &/o more instructions.

[LaurieAG]

andWinsor15,

 

The answer is the same as the one I gave in your duplicate thread. Unless you are designing an ISA for a chip from scratch you must conform with the specs for the designated chip/support chips you are using. The registers are built in and you access them and put contents in/out and manipulate their contents through assembly language or the hexadecimal (base 16) of the binary machine code (base 2) that is equivalent to the assembly language instructions, addresses and contents used.

 

 

Basically it would be opcode length + address length + register contents length for both.

http://en.wikipedia.org/wiki/Assembly_language

The practical assessment part of the microprocessors subject I studied at university involved creating hex code (from assembly language) that would be keyed into a Motorola chip to create a program that would accept 2x2 digit numbers from the keypad (displayed on the 7 segment display), multiply those two numbers together and then output the result to the 7 segment display, all within 256 bytes.

Edited March 16, 2013 by LaurieAG