Computer Organization - Cache/Mem Architecture

[smithisize]

Hi everyone. So, I've got some homework that looks like this:

 

A byte-addressable CPU with 32 address lines is interfaced to a 32kB direct mapped cache. The

cache is organized with a block size of 64B.

a) [2] How many blocks does the cache contain?

b) [2] How many bits are in the tag field?

 

And I'm searching through my book and cannot find the differentiation between address lines and blocks.

 

But, regardless, I have two attempts at solving part A):

 

Attempt 1: the cache is 32kB in size, and has a block size of 64B. So 32kB/64B = 512 Blocks

Attempt 2: I found a PDF online that says that if there are 32 address lines, that corresponds to 2^32 words of memory. If the block size/length is 64B and word size is 32bits, then each block holds 16 words. So 2^32 words/16 words per block = 268435456 blocks.

 

PDF http://umcs.maine.edu/~cmeadow/courses/cos335/COA04.pdf

Those are my thought processes. Which, if either, are correct? How do I find that? Because A block in a cache is one "row" if we're visualizing things, hence my 1st attempt. But, the PDF says that bit of information about address lines, which confuses me because I don't know (and can't find) where they are.

 

 

For part b, here's my though process. Assuming my first attempt at part A is correct, the cache size is 2^n=512 blocks, meaning we need an n bit index, in this case a 9 bit index. So, if 9 of the block size is 64 bytes, that is 512 bits. Meaning, 512-9 = 503 bit tag.

 

Once more I'm thrown for a loop by something else though. My book says:

The cache size is 2^n blocks, so n bits are used for the index
The block size is 2^m words or 2^(m+2) bytes, so m bits are used for the word within the block and two bits are used for the byte part of the address. Therefore, with 32-bit byte addresses, the size of the tag field is 32-(n+m+2)

 

Which leads me to think I'm completely wrong.

Hopefully someone can help clarify this all!

 

Thanks

[pwagen]

Ugh, memory. Confusing stuff. Read this and see if you agree with my reasoning:

http://codingfreak.blogspot.com/2009/03/cache-memory-fully-associative-mapped.html

 

A

While the CPU itself has 32 lines, the question is in regards to the cache. So it seems to me that we can ignore anything about the CPU and focus solely on the cache. This might be me being an idiot, but it seems your first attempt is correct.

 

B

I'm a bit unsure about A, but that's nothing compared to how I feel about B. It's been a while since I did any of this, so I will keep working on it until someone smarter than me figures it out.

[smithisize]

Thanks for the reply,

 

It turns out that you're correct, my first attempt was right. And, you're correct in saying that the 32 lines piece of information had nothing to do with it.

 

For B, I've been working on it.

 

So, in order to navigate the blocks, yes, my index needs to be 9 bits to select 1 of 512 blocks. These blocks are byte addressable. So, in order to access 1 byte out of 64, I need an additional 6 bits to select the byte being requested.
Therefore, assuming a 32 address coming from the CPU, the number of bits allocated to my tag should be 32 - 9 - 6 or 32-15 which is 17 bits.

Does that make more sense? It kind of makes sense to me, but I'd love someone else's opinion.

[pwagen]

While I can't work out whether it's actually right, it does make a lot of sense. And I'm guessing n and m in the quote from your book are the number of bits needed to select the blocks and bytes. What I don't understand is this though:

 

 

Therefore, with 32-bit byte addresses, the size of the tag field is 32-(n+m+2)

 

If n and m are 9 and 6, where does +2 come from, and should the answer then be 15 bits?

[smithisize]

While I can't work out whether it's actually right, it does make a lot of sense. And I'm guessing n and m in the quote from your book are the number of bits needed to select the blocks and bytes. What I don't understand is this though:

 

 

 

If n and m are 9 and 6, where does +2 come from, and should the answer then be 15 bits?

 

In the book, they were dealing with word-addressable blocks. That difference is the only reason I can see where the +2 might come from. I don't think we need it, because it makes sense to me that to select 1 of 512 blocks, I need 9 bits, and within those blocks, to select 1 of 64 bytes, I need 6 bits. The books equation just doesn't make sense, and isn't well explained.