Calculating Cache hit rate and Assembly Language

[Obeng]

Please can anyone help me solve this?

 

1. As an example, consider a two-level cache in which the L1 hit time is 5 ns, the L2 hit time is 20 ns, and the L2 miss time is 100 ns. There are 10,000 memory references of which 10 causes L2 misses and 90 causes L1 misses. Compute the hit ratios of the L1 and L2 caches and the overall effective access time

 

2. Write an assembly language program, which adds three numbers and stores the result at ADD. The numbers are defined at three consecutive locations

[EdEarl]

First, we help with homework, but not do it for you. Thus, you should have posted an attempted solution already.

 

Second, you do not specify what the assembly language instructions are, every machine is different. Thus, you have not given enough information to do problem 2.

 

I don't know if you have given enough information to solve 1; I would prefer to read the machine manual and look at any timing sequences before attempting a solution. Is this machine hypothetical or real; if real, which one. Do you have a link to the manual?

[Obeng]

Please the machine is hypothetical, we've not started with machine language yet but this is a research we are to do before we start.

[BearOfNH]

1. As an example, consider a two-level cache in which the L1 hit time is 5 ns, the L2 hit time is 20 ns, and the L2 miss time is 100 ns. There are 10,000 memory references of which 10 causes L2 misses and 90 causes L1 misses. Compute the hit ratios of the L1 and L2 caches and the overall effective access time

 

2. Write an assembly language program, which adds three numbers and stores the result at ADD. The numbers are defined at three consecutive locations

 

1. So for 10,000 memory references there are 9910 L1 hits, or 49,550 ns.

 

The remaining 90 accesses break down into 80 L2 hits (totaling 1600 ns.) and 10 L2 misses (totaling 1000 ns.) for a total of 52150 ns. spent accessing memory.

 

That should get you started. Don't let your teacher say there are only 9900 L1 hits...to get an L2 miss you need an L1 miss, and there are only 90 of those, not 100.

 

2. As Ed said, since we don't know the machine we can't help at the moment. I hope to heck your imaginary machine is at least 64 bits wide.