Computer architecture question about tag and cache

[Chicca94]

I don't know if this is the right place where I can post my question. I'm studying computer architecture for an exam in September but I find some question in the program and I don't know how to answer to them. I tried to search on Internet but I did not find anything. The questions are:

 

Given the number of sets, the number of lines per set, the number of words per

line and the number of cells per word, draw the structure of a cache (show tags,

valid bits and data structured in sets, lines, words and cells).

 

Given the number of sets, the number of lines per set, the number of words per line

and the number of cells per word, and assuming the LRU (least recently used)

replacement policy, simulate a sequence of LOAD instructions accessing that cache.

Hope that someone can help me. Thanks a lot

[fiveworlds]

Here's a different question give me one example of where a modest income person would ever be able to use this. Think rationally here the cache is on the processing chip. The processing chip is made by robots. When will you be able to afford robots?

 

Edited July 5, 2014 by fiveworlds

[Chicca94]

Noooo. How it's made? I love this program. I will try to understand something. Thanks

[fiveworlds]

62-Core Xeon Phi 5,000,000,000 2012 Intel 22 nm

 

 

 

Thats 5,000,000,000 transistors on one chip same company it's not a recent count but you can have a look http://en.wikipedia.org/wiki/Transistor_count They'll be making single atom transistors fairly shortly. See they had this law Moore's Law that the power of computers would double every set number of years because nanotechnology would advance but it doesn't get much smaller than an atom.

Edited July 5, 2014 by fiveworlds

[Chicca94]

Is there a particular way to represent also valid word and tag? Also there is the second question that I don't understand