Help with NMOS depletion load intuition

[CasualKilla]

I need some help intuiting the input vs output characteristic for the NMOS depletion load circuit. For example, I can see why the driver should start off saturated then move towards non-sat as Vinput increases, but I cannot see why the load should start off non-sat. Additionally, if we assume the output resistances to be large, then the driver switches to non-sat and the load switches to sat at the exact input voltage (which doesn't seem obvious to me).

 

I have attached some figures to illustrate the problem.

Edited May 24, 2015 by CasualKilla

[Enthalpy]

Nmos logic has disappeared for the eternity to come, together with depletion loads. It was nearly extinct when I studied 30 years ago.

 

Depleted Mos "saturate" with a big drain-to gate voltage, as opposed to bipolars. Bad wording choice, we must live with that.

 

When the output is high (input low), the load transistor conducts less than its saturation current, hence is not saturated.

When the output is low, the load transistor conducts its Idss and is saturated.

Well, at least if the circuit was designed normally. If the supply voltage doesn't suffice you'll get bizarre ways of operation. Or if a huge dosis of ionizing rays lets the Vt drift, and so on.