Radiofrequency Analog-to-Digital Converter

[Enthalpy]

Hello everybody!

This shall be an analog-to-digital converter (Adc) for radiofrequencies. Up to now they're "Flash" converters or similar, whose dynamic range doesn't fulfil radiofrequency desires, because their complexity and the offset and 1/F noise limit them, especially if using the fastest components.

My proposal instead uses several stages that are Ac-coupled to remove the offset and 1/F noise, where every stage contributes the digital output and has a modest gain. It is similar to a "logarithmic amplifier" (not the one with an op amp, but the amplifier-detector formerly used in radars and spectrum analyzers) like the LT5538
http://www.linear.com/docs/26333block diagram on page 7

Logarithmic amplifiers cumulate an absolute value of the local amplitude over all stages. As opposed, my converter outputs "strongly negative / weak / strongly positive" at each stage. Consequently, the converter's output is a mu-law if all stages have equal gains
https://en.wikipedia.org/wiki/%CE%9C-law_algorithm
which fits a wide dynamic range. Some logic determines which amplifier stage is the first to make the signal stronger than the threshold; together with the sign, this is the raw output data.

More stages with less individual gain (like 2, or 1.25, or even less) give a finer conversion. Software downstream can represent the mu-law data in a linear way, for instance as float numbers, and optionally adjust the values in accordance to the identified thresholds to improve the conversion linearity.

No sample-and-hold is needed. The amplifier chain is extremely fast; the synchronizing flip-flops limit the speed rather. The clock can be dispatched to follow the amplifier chain's delays, as in Analog Devices' old patent for logarithmic amplifiers. Some in-package logic can pack the data to reduce the outside wiring.

In this example (two stages only, without the flip-flops nor logic), bipolars ease the stage comparators, but many diagrams are possible, with fast Fet too:

The differential triplet in the example has the Bias' high enough that the current flows through the central transistor when the local signal is weak; a signal strong enough at this stage would make one base positive enough to lower one output depending on the signal's sign.

Only stability limits the dynamic range. Differential operation helps, as the SO41 showed, and proper supply wiring in the chip too. Grounding the positive supply should improve a bit, and separate supply regulators per stage as well. If breadboarding, beware the Bfr90 and others demand their emitter grounded.

Marc Schaefer, aka Enthalpy

[Enthalpy]

In a variant, each amplifier stage can have several digital outputs, so there are fewer amplifier stages, each with a gain less small.

 

The example diagram would have as many differential triplets, (unrepresented) flip-flops and gates for the same number of logic outputs, but grouped on fewer amplifier stages. Darlingtons would minimize interactions. Varied BiasN at differential triplets of the same amplifier stage makes them sensitive to varied thresholds.

Marc Schaefer, aka Enthalpy